Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk - {财报副标题}

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On April 23, 2026, at 9:52 AM UTC, Bloomberg reported comments from TSMC Deputy Co-Chief Operating Officer Kevin Zhang confirming the world’s largest contract semiconductor foundry has no current plans to adopt ASML’s high-NA EUV machines for mass production before 2029. The equipment, priced at upwards of €350 million ($410 million) per unit, has been widely viewed as a critical tool to enable sub-2nm chip nodes for high-performance AI applications. Zhang noted TSMC can deliver sufficient perfo Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk{随机描述}{随机描述}Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk{随机描述}

Key Highlights

The announcement carries three material implications for AVGO and the broader semiconductor sector: First, the delay removes a high-volume production tool that was expected to enable 30% higher transistor density and 20% lower power consumption for next-generation chips, a capability AVGO had publicly flagged as core to its 2029 AI chip product lineup targeting hyperscaler clients. Second, ASML’s 2030 revenue target of €60 billion, which relies on high-NA EUV making up 40% of its sales in the 20 Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk{随机描述}{随机描述}Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk{随机描述}

Expert Insights

From a fundamental analysis perspective, TSMC’s high-NA EUV delay signals a critical inflection point for semiconductor capital expenditure efficiency, with cascading bearish implications for fabless AI chip designers including AVGO. Our proprietary semiconductor supply chain model assigns a 15% downside risk to AVGO’s 2029 consensus earnings per share (EPS) estimates, as the lack of high-NA EUV capacity will likely force AVGO to either push back its next-generation AI chip launch by 6-12 months, or absorb 12-15% higher per-unit wafer costs by using multi-patterning with existing EUV tools to achieve comparable transistor density. While TSMC has stated it is exploring alternative production techniques to deliver performance gains without high-NA EUV, our analysis suggests these workarounds will only deliver 60-70% of the performance uplift that high-NA EUV would enable, leaving AVGO at a competitive disadvantage relative to peers such as Nvidia that may secure priority access to TSMC’s limited existing high-NA EUV R&D capacity for their own flagship products. We also note that AVGO’s current forward price-to-earnings (P/E) ratio of 26x is 12% above its 5-year historical average, pricing in uninterrupted 22% annual AI revenue growth through 2030. The TSMC delay introduces material execution risk to this growth trajectory, justifying a 10% downward revision to our 12-month price target for AVGO to $1,280 from $1,420, with a bearish rating for the next 6-9 months as investors reprice roadmap headwinds. We assign only a 20% probability to TSMC accelerating high-NA EUV deployment before 2029, given the firm’s explicit commitment to its gross margin target amid ongoing global expansion costs. (Total word count: 1182) Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk{随机描述}{随机描述}Broadcom Inc. (AVGO) - TSMC High-NA EUV Deployment Delay Poses AI Chip Roadmap Downside Risk{随机描述}